82510 sy 20100803-s00005 no.a1823-1/6 http://onsemi.com semiconductor components industries, llc, 2013 june, 2013 LV0221CS overview the LV0221CS is a front monitor optoelectronic ic for optical pickups that has a built-in photo diode compatible with three waveforms. LV0221CS is sm all size and type csp packages. functions ? pin photodiode compatible with three wavelengths incorporated. ? gain adjustment (-6db to +6db in 256 steps) through serial communication. ? amplifier to amplify differential output. specifications maximum ratings at ta = 25 c parameter symbol conditions ratings unit maximum supply voltage v cc 6v allowable power dissipation pd1 glass epoxy one-side substrate 55mm 45mm 0.8mm copper foil area (about 80%), ta=75 ? c 136 mw pd2 glass epoxy one-side substrate 55mm 45mm 0.8mm copper foil area (head: about 85% tail: about 90%), ta=75 ? c 100 mw operating temperature topr -20 to +85 ? c storage temperature tstg -40 to +100 ? c recommended operating conditions at ta = 25 c parameter symbol conditions ratings unit min typ max operating supply voltage v cc 4.5 5 5.5 v output load capacitance c o 12 20 33 pf output load resistance z o 3 k cmos ic front monitor oe-ic for optical pickups ordering number : ena1823 stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above the recommended oper ating conditions is not implied. extended exposure to stresses above the recommended operating conditions may affect device reliabili ty.
LV0221CS no.a1823-2/6 electrical characteristics at ta = 25 c, v cc = 5v, rl=6k , cl=20pf parameter symbol conditions ratings unit min typ max current dissipation i cc 18 23.4 ma sleep current islp 1 ma output voltage when shielded v c at shielding 1.8 2.0 2.2 v output offset voltage vofs at shielding, voltage between vop-von -30 0 30 mv temperature dependence of offset voltage *1 vofs ta=-10 to +85 ? c -60 0 60 v/ ? c optical output voltage *1 voltage between vop-von vlc low gain, =780nm, g=0db 0.21 0.262 0.31 mv/ w vld low gain, =650nm, g=0db 0.22 0.275 0.33 mv/ w vlb low gain, =405nm, g=0db 0.14 0.172 0.21 mv/ w vmc middle gain, =780nm, g=0db 0.66 0.83 0.99 mv/ w vmd middle gain, =650nm, g=0db 0.70 0.87 1.05 mv/ w vmb middle gain, =405nm, g=0db 0.43 0.54 0.65 mv/ w vhc high gain, =780nm, g=0db 1.97 2.46 2.95 mv/ w vhd high gain, =650nm, g=0db 2.07 2.58 3.10 mv/ w vhb high gain, =405nm, g=0db 1.29 1.62 1.94 mv/ w light output voltage adjustment range *1 g g=0db refere nce, absolute value of adj ustment width 5.5 6.0 6.5 db d range *1 vod voltage between vop-von 1700 2200 mv frequency characteristics *1, *2 fcc -3db(1mhz reference), =780nm light input = 40 w(dc) + 20 w(ac) 50 75 mhz fcd -3db(1mhz reference), =650nm light input = 40 w(dc) + 20 w(ac) 60 85 mhz fcb -3db(1mhz reference), =405nm light input = 40 w(dc) + 20 w(ac) 60 85 mhz settling time *1 tset 15 ns response time *1 tr, tf vo=0.9vp-p, output level 10 to 90% fc=10mhz, duty=50% 10 ns overshoot *1 ovst vo=0.9vp-p 15 % undershoot *1 unst vo=0.9vp-p 15 % linearity *1 lin at output voltage 0.5v and 1.0v (between vop-von) -1 0 1 % light-output voltage temperature dependence voltage between vop-von *1, *3 tc =780nm, 25 ? c reference 10 13 16 % td =650nm, 25 ? c reference 0 3 6 % tb =405nm, 25 ? c reference 0 3 6 % light-output voltage s pectral sensitivity voltage between vop-von *1 vf =785nm 10nm -0.8 0.1 %/nm =660nm 10nm -0.4 0.4 %/nm =405nm 10nm 0 1.2 %/nm step-step voltage ratio *1 dg (vn-vn-1) / vn *100 *4 deviation from the ideal curve of above equation -3 0 3 % item with *1 mark indicate the design reference value. item with *2 mark indicate the frequency characteristics when vop and von are applied individually. the frequency characteristics are for the case of high / middle / low gain and for the case when the output voltage adjustment range is -6 to +6db item with *3 mark indicates the temperature dependence for the ca se of high / middle / low gain and for the case when the tempe rature is 25 to 85 ? c for the output voltage adjustment range of -6 to +6db vn in item with *4 mark is vn = (sensitivity / 2 ) 5400 / (5400-16 gcastep ) light intensity ( w) gca = gain control amplifier
LV0221CS no.a1823-3/6 package dimensions unit : mm (typ) 3402 pin assignment pin no. pin name function 1a sdio serial communication data pin 1b vop positive side output pin 1c von negative side output pin 2a sclk serial communication clock pin 2c ssel register selection pin ssel = low, open : address 00 to 0fh used ssel = high : address 10 to 1fh used 3a sen serial communication enable pin 3b gnd gnd pin 3c v cc power supply voltage pin pd assignment *pd size for reference to be used for design sen gnd v cc sclk ssel sdio vop von top view 3 2 1 a b c 1.75mm 1.75mm 0.875mm 0.875mm center of pd sanyo : odcsp8(1.75x1.75) 0.55 0.55 0.1 (0.52) 0.68 max 1.75 1.75 0.875 0.875 top view side view side view bottom view 0.275 123 a b c 123 c b a
LV0221CS no.a1823-4/6 block diagram and test circuit diagram resister table enable selection of the register group from the ssel pin. ssel = low, open address 7 6 5 4 3 2 1 0 name 00h power iv gain sel gain sel default 00 00 00 x x value 11: power on 00 01 10: sleep 00 01: high 10: middle 11: low 00 01: bd 10: dvd 11: cd name 01h bd gain default 1 1 1 1 1 1 1 1 value 00000000 to 11111111 name 02h dvd gain default 1 1 1 1 1 1 1 1 value 00000000 to 11111111 name 03h cd gain default 1 1 1 1 1 1 1 1 value 00000000 to 11111111 name 0eh test1 (*1) name 0fh test2 (*1) ssel = high address 7 6 5 4 3 2 1 0 name 10h power iv gain sel gain sel default 00 00 00 x x value 11: power on 00 01 10: sleep 00 01: high 10: middle 11: low 00 01: bd 10: dvd 11: cd name 11h bd gain default 1 1 1 1 1 1 1 1 value 00000000 to 11111111 name 12h dvd gain default 1 1 1 1 1 1 1 1 value 00000000 to 11111111 name 13h cd gain default 1 1 1 1 1 1 1 1 value 00000000 to 11111111 name 1eh test1 (*1) name 1fh test2 (*1) *1 test1 and test2 are either the time when power is applied or ? 00000000? is set. do not attempt to change ?00000000? during o peration. ?00000000? is returned when reading is made. *2 no problem in terms of operation occurs even when wr iting is made to the address 04h to 0dh and 14h to 1dh. ?00000000? is returned when this address is read. + - vref low middle high + - vref serial sen sclk sdio ssel bias regulator vref v cc control 20pf vo+ vo- 20pf v cc gnd
LV0221CS no.a1823-5/6 serial protocol sdio pin load / cl=20pf (the table below shows the design reference value.) parameter symbol min. typ. max. unit scl clock frequency write f scl 0 10 mhz scl clock frequency read f scl 0 4 mhz sdio data setup time t dsu 50 ns sdio data hold time t dho 50 ns sdio output delay t ddly 10 80 ns sen ?h? period t enh 1.6 s sen ?l? period t enl 200 ns scl rise time after sen rise t st a 60 ns sen fall time after final scl rise t sto 100 ns serial input ?h? voltage v i h 2.4 v serial input ?l? voltage v i l 0.6 v sdio output ?h? voltage v o h 2.5 2.9 3.3 v sdio output ?l? voltage v o l 0 0.3 0.8 v a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 1 2 3 4 5 6 789 10 11 12 13 14 15 16 msb lsb msb lsb mode address data (output data from host) (host) sen (host) sclk (host) sdio a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 12 3 4 5 6 789 10 11 12 13 14 15 16 msb lsb msb lsb mode address data (output data from host) (host) sen (host) sclk (host) sdio sdio write timing chart read timing chart t sta t enh (host) sen (host) sclk (host) sdio (host) sen (host) sclk (host) sdio sdio t enl t sto t dsu t dho t ddly write read
LV0221CS ps no.a1823-6/6 pin type equivalent circuit diagram sdio input output vop von output sclk ssel sen input 3v 3v on semiconductor and the on logo are registered trademarks of semiconductor components industries, llc (scillc). scillc owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. a listing of scillc?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent-marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc mak es no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability ar ising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequentia l or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s techn ical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorize d for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other appli cation in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of persona l injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture o fthe part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws a nd is not for resale in any manner.
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